Most memory circuits are “single port” memory circuits that can only be read from or written to by a single memory using entity. For example, the standard six-transistor (6T) static random access memory (SRAM) cell only has a single memory port such that only one read operation or one write operation can be handled at a time. For many applications it is desirable to have “multi-port” memory systems where more than one memory using entity may concurrently access the same memory cell. For example, in a multi-core processor system it is advantageous to allow multiple processor cores to be able access the contents of the same memory address concurrently. Allowing concurrent access prevents processing “stalls” wherein a processor core must wait for another memory access operation to complete before that processor core can access data from the desired memory location.
To allow two (or more) concurrent memory access operations, the fundamental memory cell circuitry may be altered to include additional physical memory port circuits. For example, the standard single-port 6T SRAM cell may be transformed into a two-port memory cell by adding two more transistors that provide a second port for accessing the memory cell. With a second memory port, two different memory using entities can read from the same 8T SRAM cell at the same time.
Adding two additional transistors to implement a second port increases the physical size of the memory cell circuit. Furthermore, due to the risk of losing memory bit stored in the SRAM memory cell, certain transistors in the two port 8T SRAM cell must be made much larger thus further increasing the size of the two port 8T SRAM cell. Thus, adding a second memory port can significantly reduce the memory density (memory bits per integrated circuit area) of the memory system. In addition to the increased circuit size, multi-port memory cells will consume more power.
To create the most efficient multi-port memory systems in terms of memory density, performance, and power consumption, integrated circuit designers must often resort to designing custom multi-port memory arrays. Designing a custom multi-port memory system is a very costly and time consuming process. The only alternative is to allow synthesis tools to create multi-port memory as needed but the multi-port memory created by synthesis tools tends to be very inefficient. Therefore, it would be desirable to have alternative multi-port memory cell designs and systems for creating multi-port memory.